Siemens EDA

This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.

How should you address the monitoring and resource challenges in maintaining security for Linux devices.

Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.

The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.

Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.

ESD has always been a major issue but with increasing densities and growing die sizes it is becoming a higher order concern. Automation and vizualization can help manage the task.

The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.

How the use of declarative, constraint-based descriptions can help you focus command sequences on areas of interest.

P2P (point-to-point) resistance is fundamental to IC reliability verification. Handle it more efficiently with detailed, automated path layout analysis.

You cannot break your operating system choice down in something as simple as a flowchart but there are some headline criteria you should think about.