EDA

April 22, 2015

Thursday returns as DAC training day

The Design Automation Conference in San Francisco this year will again feature a day of half-day training courses provided by Doulos on Thursday, June 11 .
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April 22, 2015

Fusion core targets voice-activated devices

Cadence has launched a processor core aimed at ‘always on’ signal-processing applications such as voice detection and recognition for wearables.
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April 22, 2015

Mentor tool streamlines multi-corner parasitic extraction

Mentor Graphics has launched Calibre xACT, a tool that uses deterministic algorithms to extract parasitics from complex finFET and other nanometer processes.
April 21, 2015

Are you ready for design for crime?

Designers will need to take crime into account as part of their design signoff process, Wally Rhines argued in his keynote at Mentor Graphics' U2U San Jose 2015 conference.
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April 21, 2015

Cadence updates OrCAD line with additions for PCB manufacturability and integrity

Cadence Design Systems has added five products to its OrCAD line of PCB-design tools that cover manufacturability, signal integrity and management, and introduced three feature updates.
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April 9, 2015

Mentor’s 2015 Valley User2User is less than two weeks away

IoT-themed keynotes from Mentor's Wally Rhines and Qualcomm's Karim Arabi headline vendor's User2User conference on April 21.
March 24, 2015

Mentor unites chip-to-package flow with Xpedition Package Integrator

Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.
March 18, 2015

ARM and Cadence agree to share IP access

ARM and Cadence have signed a deal that provides the IP teams at both companies with access to each other's cores.
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March 10, 2015

Synopsys claims finFET leadership

Synopsys claims its tools have enabled 90% of finFET designs currently going into volume production
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March 10, 2015

Cadence reworks implementation for both finFET and older processes

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
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