Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
Frank Schirrmeister, senior director at Cadence, claimed the combination can deliver 20 per cent better power, performance and area (PPA) than hand-coded RTL for a variety of designs. “It’s better than RTL with respect to area in most instances.
“HLS over the years has had this notion that it was only useful for datapaths. Now it is also for control. And it has also been integrated into the flows and logic synthesis for things like ECOs. You can do ECOs and trace them all the way back up,” Schirrmeister added, noting there are now significant drivers for moving to HLS.
“People are moving more of their verification work upwards, to the transaction level. And IP reuse at a higher level has emerged as a critical requirement, using resynthesis for different implementation.”
The combination of technologies available in the Stratus has led Cadence to claim that the one HLS environment can now be used across an entire SoC design. Integration with Encounter RTL Compiler and Conformal CEO Designer allow both physically aware synthesis and ECO-aware high-level synthesis to minimize the impact of ECO-driven changes.
Ray McConnell, CTO of Blu Wireless Technology said the company has used high-level synthesis through Stratus in the development of its millimetre-wave wireless interface chips. “We can now have a working prototype of a complete multi-gigabit modem with a millimeter-wave beam-steering antenna available when we’re doing the integration and system and software validation. Previously, we would have had to use poor approximations for early validation. Having an early working prototype is having a significant business impact.”