EDA

RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.

Siemens PLM strategy VP Stefan Jockusch will keynote on digital twins in the automotive sector at next month's conference in Shanghai.

Popular Verification Academy manual revamped and updated to bring it more closely in line with IEEE 1800.2 UVM and reflect the increasing use of emulation.

Registration has opened for the first ES Design West exhibition, which takes place alongside Semicon West in San Francisco in July.

The trend toward Level 5 fully autonomous vehicles poses major complexity, cost and change issues that Generative Design flows aim to address.

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.

Do China's ambitions as a world-class innovator face fundamental challenges as a result of the sector's existing economic infrastructure?

OneSpin will focus at DVCon on its formal integrity verification platform for the RISC-V open-source which aims to speed up the core's adoption. The company will also feature the solution with a partner at EmbeddedWorld.

The company will share a stand at EmbeddedWorld in Nuremberg with its sister Siemens division Polarion and has seven papers across the technical program.