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The Multicore Association has launched a guide to programming multicore systems in C and C++.

A team effort between three French companies has resulted in the launch of an FPGA prototyping system that is intended to provide emulation of designs with up to 25 million ASIC gates.

Cadence Design Systems is to buy Cosmic Circuits Private Limited, a developer of analog and mixed signal intellectual property (IP) cores.

GlobalFoundries has signed deals to let the foundry offer power-saving clocks, a massively parallel floating-point processor and interface IP from Rambus. They are "uncommon solutions" to come from a foundry, the company claims.

Mentor's HyperLynx gets speed and accuracy enhancements, as well as more embedded help, to speed up fast board design

Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.

14nm finFET test-chip designs are moving through Samsung's fab as ARM, Cadence Design Systems and Synopsys continue to check their flows on the new process.

Altera has cut a deal with ARM to bring unified debug support to the FPGA fabric and Cortex-A9 processors inside the Cyclone SoC products, using a specialized version of ARM’s DS5 tool.

Mears Technologies and UC Berkeley describe at IEDM 2012 how oxygen in a silicon superlattice could boost performance beyond strained silicon at 14nm.

Embedded software engineers need to focus on power optimization in their code much earlier and more comprehensively than many of them do today, says Mentor Graphics technologist Colin Walls.