5G and automotive provide applications focus for DVCon Europe

By Chris Edwards |  No Comments  |  Posted: September 22, 2017
Topics/Categories: Blog - EDA, Embedded  |  Tags: , , , , , ,

The massive complexity of 5G and automotive systems and the need for advanced verification techniques set the scene for DVCon Europe this year.

At the conference, which takes place in Munich, Germany on October 16 and 17, 2017, keynotes and special sessions will underline the challenges that face developers of upcoming 5G networks and motor vehicles with high levels autonomy.

The verification requirements are getting more intense in areas such as automotive, says general chair Oliver Bell, not just in terms of functional safety but security and the problems of dealing with such complex systems.

Keynote speaker Berthold Hellenthal of Audi will cover verification topics such as the use of virtual prototyping in automotive designs.

Bell says: “In terms of cycle times, the automotive companies are moving a traditionally long development cycle to one that is more of a consumer-type cycle. But at the same time, they are not giving up on the requirements for safety and security.”

“We are seeing more model-driven engineering approaches being used,” says Martin Barnasconi, DVCon Europe tutorial chair. “You have models being used in parallel for hardware, software and system-level development.”

A special session on 5G on Tuesday, October 17 will feature speakers from Intel, Nokia and Rohde & Schwarz. The session, says Bell, will help highlight “the need for verification of the complete systems, with software complexity being a big driver”.

With keynotes from Audi and Bosch as well as the 5G session reflecting the applications drivers for advanced verification, the technical sessions and tutorials at DVCon Europe will cover how users and vendors are attacking various parts of the verification puzzle.

Matthias Bauer, DVCon Europe program chair, says the committee received 39 papers this year and accepted 24. “The quality is very high,” he claims. “There are fewer papers on UVM. Instead, there is a better mix, going from formal verification to functional coverage and IP-XACT. We have analog/mixed-signal and power verification papers and some papers on debugging.”

One of the themes of this year’s DVCon Europe is the use of automation in verification, using description languages such as IP-XACT to generate tests automatically. “Papers show how IP-XACT can be used as a backbone for the data model,” Bauer says. A paper from Texas Instruments and a tutorial by SyoSil show how, for example, IP-XACT can be used to help build register models in UVM.

“Use of IP-XACT is really picking up in the UVM space,” adds Barnasconi.

Other papers will look at techniques such as the use of big-data analysis tools for automating portions of verification. For example, a paper from Mentor Graphics describes the use of MapReduce to help speed up the analysis of functional coverage. A tutorial on Monday focuses on the research of seven German universities working with industry partners on automated firmware generation and validation.

A look into the future of system-level design will be available the day after DVCon Europe in Munich, with Accellera’s SystemC Evolution Day.

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