low-power design

August 20, 2014

ARM explores multithreaded core as alternative to GPU computing

ARM is working on a heavily multithreaded version of its processor core to see if it can provide a more convenient alternative to GPUs.
Article  |  Topics: Blog - Embedded  |  Tags: , , , , , , ,   |  Organizations:
July 3, 2014

IEA takes aim at network-device energy consumption

The International Energy Agency (IEA) has turned its attention to slashing the electricity demands of network-attached devices with a report that says manufacturers and service providers need to look at changes to protocols and features such as energy harvesting.
December 16, 2013

TSMC hints at glass interposer for mobile SoCs

Glass may be the high frequency interposer option given silicon concerns about power and noise. TSMC adds another pathfinder to its 3D arsenal.
Article  |  Topics: Commentary, Conferences, Design to Silicon, Blog - EDA  |  Tags: , , , ,   |  Organizations:
December 16, 2013

Qualcomm’s take on preserving Moore’s Law economics

Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
November 12, 2013

Cadence ties IR drop into static timing analysis

Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
May 30, 2013

Latest version of IEEE 1801/UPF available for free

The latest revision of the IEEE 1801 Unified Power Format standard for verifying low-power designs has been made available through the IEEE Get Program.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,

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