Cadence adds floating point to Fusion
Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
Author Archives: Chris Edwards
IEDM alters schedule to keep abreast of process updates
The International Electron Device Meeting has pushed back the deadline for its papers to get the latest developments in process and device design into the December conference.
The IoT dream behind SoftBank’s ARM purchase
SoftBank cites IoT as its main reason for buying ARM, but could it change the relationship between customers and the processor designer?
EEMBC looks into heterogeneous compute
EEMBC has turned its attention to heterogeneous computing with plans to create a new set of benchmarks.
DTCO points to sub-10nm optimizations
DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
What’s the shortest time in the universe?
“It’s the time between putting out an open-source ARM core and getting a letter from an ARM lawyer,” says UC Berkeley professor Krste Asanovic. So, some design teams are turning to IP that started out as open source to provide more scope for experimentation.
DFT to expand its role for long-term yield
Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
2D tools adapt to create smaller monolithic 3DIC designs
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
Minimize memory moves for greener data centers
Deep pipelines and dynamic memory sharing may provide the key to the development of faster and more efficient server-farm blades as the focus in hardware design moves to augmenting conventional processors with specialized accelerators.
ARM accelerates POP deployment for Cortex-A73
A faster implementation program for the POP support IP for ARM's cores has delivered a 16nm finFET package for the Cortex-A73 shortly after the core's Computex launch.