ARM accelerates POP deployment for Cortex-A73

By Chris Edwards |  No Comments  |  Posted: June 7, 2016
Topics/Categories: Blog - EDA, IP  |  Tags: , ,  | Organizations:

ARM has sped up the development of its POP IP to bring versions out much closer to the public launch of the processors the designs are meant to support and help inform micro-architectural choices. The result of the program is a version of the Cortex-A73 for TSMC’s 16FFC process a week after the core’s launch at Computex.

Will Abbey, general manager of the physical IP group at ARM, said: “For a number of years we were working hard to get to a point where, as we make the leading core available, we would have a POP IP coincident with that launch.”

Abbey said by having an implementation team working side by side with microarchitecture, the two groups were able to explore more tradeoffs to aid speed or layout efficiency. In the design of the Bifrost GPU architecture, microarchitecture team decided to change the register file location within the shader cores to be easier to place and route on finFET processes where high-speed interconnect resource is more restricted.

The constraints and design files for the A73 POP are intended to deliver a 1V processor running at up to 3GHz on the TSMC process or a lower-power version operating at 0.72V and hitting 1.8GHz. Abbey said the company taped out its first A73 in early May able to run at up to 2.86GHz. “So we are confident that the final version will deliver 3GHz.”

The pilot A73 is also being used to test and demonstrate a new type of state-retention flip-flop intended for aggressive power gating techniques that occupies less area than previous implementations. “It offers very fast shutdown and wakeup. We spend a lot of time innovating around this design so we could bring it in with negligible area impact,” Abbey claimed.

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