Ceva aims to displace ARM in IoT nodes with combo processor
Ceva has decided to take its VLIW architecture into the world of IoT sensor nodes and smart wearables with the launch of the X1 processor core.
Author Archives: Chris Edwards
Cadence packages VIP for ten protocols
Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
Ceva adds hardware to speed up deep learning
Ceva has launched the fifth generation of its vision-oriented DSP core family with an architecture tuned for the fast-growing area of convolutional neural networks and deep learning.
UltraSoC to support RISC-V
UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
Debut for safety-critical ARMv8 core
ARM has launched the first of its Cortex-R series of processors to be based on the v8R architecture, providing greater protection for software tasks from each other.
GlobalFoundries ports MRAM to 22nm FD-SOI
GlobalFoundries has introduced an embedded-MRAM option for its 22nm FD-SOI process: the 22FDX platform.
DVCon Europe to examine role of UVM, SystemC in system-level verification
DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Cadence building photonics environment around Virtuoso
Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
EEMBC updates automotive benchmark for scalability tests
EEMBC has released version 2.0 of its suite for measuring the performance of automotive powertrain tasks on multicore processors.
SystemC materials move to Apache 2.0 license
Accellera has moved to an Apache 2.0 open-source license for all of the supplementary materials for its SystemC library.