Blog Topics

Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.

German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.

The Multicore Association has started work on the second version of its SHIM performance-modeling standard for SoCs.

On-demand seminar explains how to exploit recently announced integration of Tanner and Eldo suites for sensor, IoT and other design types.

Work by the Multicore Association to provide a standard way for applications running on different processors to communicate with each other is leading to active implementations.

Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.

ARM has launched the first of a series of Cortex-M series microcontrollers based on the V8M architecture that incorporate the Trustzone security mechanism.

A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.

At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.

Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.