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At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.

Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.

Catch up with the vendor's plans for the ARM technical conference in Santa Clara later this month.

Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.

Achronix has decided to offer the FPGA technology it has developed as a set of embeddable cores.

Ceva has decided to take its VLIW architecture into the world of IoT sensor nodes and smart wearables with the launch of the X1 processor core.

Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.

Ceva has launched the fifth generation of its vision-oriented DSP core family with an architecture tuned for the fast-growing area of convolutional neural networks and deep learning.

UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.

ARM has launched the first of its Cortex-R series of processors to be based on the v8R architecture, providing greater protection for software tasks from each other.