DRC

April 26, 2024
Yield Loss

PID yield loss countered by path-based antenna verification

Plasma induced damage (PID) in gate oxide is a threat to MOSFET circuit yield and reliability. How can you effectively combat this issue?
Article  |  Topics: Uncategorized  |  Tags: , , , ,   |  Organizations:
October 19, 2023
Neel Natekar is a senior product engineer in the Design to Silicon division of Siemens Digital Industries Software. Prior to joining Siemens, Neel worked as a design engineer focusing on power delivery solutions for custom CPUs. He received a B.Eng. in Electronics and Telecommunications from the University of Mumbai, and an M.S. in Electrical Engineering, Circuits and Microsystems from the University of Michigan.

Simplify and accelerate PV debug using default results data views

Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.
Expert Insight  |  Topics: EDA - DFM, - EDA Topics, EDA - Verification  |  Tags: , , , ,   |  Organizations:
May 10, 2022
Coordinate-based checks feature

A quick and easy way to calculate P2P resistance and current density

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
September 13, 2021
Swathi Rangarajan is a principal product engineer in the Calibre Design Solutions division of Siemens Digital Industries Software, supporting the Calibre RealTime platform. She focuses on in-design sign-off Calibre DRC checking in custom and digital design tools. Before joining Siemens, Swathi was an application engineer focusing on custom and digital design tool suites. Swathi received her BS in electronics and communication engineering from India, and her MS in engineering from San Jose State University

Hit your tapeout schedules with in-design signoff DRC

Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
Expert Insight  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , ,   |  Organizations:
May 31, 2021
Srinivas Velivala is a principal product manager with Calibre Design Solutions in Siemens EDA, a part of Siemens Digital Industries Software. His primary focus is the development of Calibre integration and interface tools and technologies. Before joining Siemens EDA, he designed high-density SRAM compilers. In addition to more than 12 years of design and product management experience, Srinivas holds a B.S. and M.S. in Electrical and Computer Engineering.

How you can decide what level of DRC you need when you need it

Using on-demand rule checks during place-and-route boosts efficiency and design quality.
October 16, 2020
Dina Medhat - Mentor

Not using reliability check waivers? You’re wasting valuable time

Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , , ,   |  Organizations:
September 21, 2020
filler cells featim sep20

P&R filler cell insertion slowing you down? Replace it

A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , ,   |  Organizations:
August 14, 2020
John Ferguson is the product management director for Calibre DRC applications at Mentor, a Siemens BusinessHe holds a B.Sc. degree in Physics from McGill University, an M.Sc. in Applied Physics from the University of Massachusetts, and a Ph.D. in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

EDA innovation is the foundation of progress

For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
Expert Insight  |  Topics: EDA - DFM, Verification  |  Tags: , , , , , , , ,   |  Organizations:
June 9, 2020
place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
May 26, 2020
cloud computing efficiencies with calibre for physical verification

How cloud computing is now delivering efficiencies for IC design

A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors