How to optimize productivity and accuracy in IC design and verification flows

For decades, the EDA industry has pursued the goal of enabling a design automation infrastructure that can produce IC layouts (and ultimately silicon) that provide profitable yield and operational reliability while meeting performance, power, size, and other crucial design metrics. Despite significant advancements in design tools, this goal remains tantalizingly incomplete. Each new technology process introduces a new set of requirements and impacts, such as new or expanded design rules to comply with changing manufacturing requirements, new or emerging physical phenomena that impact electrical behavior, more and new interconnects and device materials, and innovative design and verification methodologies. In many cases, it is extremely challenging for the EDA industry not just to keep up with these changing demands, but also to fully predict the requirements coming in the next process or process variant. The result? Designers find themselves running more and more iterations to find solutions around unanticipated problems in their designs.

In the last few years, the focus of verification has shifted away from simply identifying problems to better enabling designers to quickly understand the underlying causes and providing them with options for faster and optimized fixes. There are three primary approaches to reducing both time per iteration and total cycle time:

1. Reduce the runtime per iteration.
2. Reduce the time needed to identify and fix the root causes of errors.
3. Reduce the total number of iterations.

Physical verification is a good example of how these strategies can help design teams save time while improving their results. Foundries generate design rule manuals and corresponding design rule checking (DRC) decks to pinpoint specific failure points in a design layout. This information is very helpful at the tail-end of the design cycle when there are a handful of individual layout errors to fix. However, during early design stages, running signoff DRC verification on layouts typically generates thousands or even millions of DRC results due to systemic floorplan or placement errors. Many are caused by missing or incomplete data that is not added until later in the process flow.

If cell abstracts are incorrect, misplaced, or improperly connected, then shorts, opens and other fundamental problems are created, which results in long runtimes and huge numbers of error results. Worse still, the resulting errors provide little insight into the placement issues that caused them. If two or more nets are shorted, antenna results are essentially meaningless, but because the cause of the error is obscured, designers must debug these huge nets anyway. Debugging these types of errors is a waste of engineering time and resources because they will disappear in later iterations as the data becomes available.

The challenge for EDA suppliers is how to enable designers to determine what to run and how to present the results, without requiring changes to the qualified foundry design rule deck. At Siemens EDA, we are enabling all three strategies by adding a combination of pre- and post-processing automation to our Calibre toolsuite. It enables faster, smarter, targeted verification during early design verification, as well as expanded automated waiver management and debugging assistance to streamline the debugging process, to improve the overall design verification flow.

Pre-processing

To enable design teams to optimize early design verification, we implemented the Calibre nmDRC Recon tool containing innovative pre-processing functionality that reduces the number of rules to check and/or reduces the layout geometries that require checking. Setting these parameters before verification begins minimizes runtimes while still enabling designers to check exactly what they need to check to find typical systemic design issues and layout mistakes.

The Calibre nmDRC Recon tool automates checking of design rules that are local in scope. These rules look for specific space, width, and enclosure issues, and generate results that are geographically close to the source of the root cause. In addition, local scope rules tend to run fast and scale very well. Some of these rules are relatively obvious simply by identifying what is not a local scope rule. Design rule checks requiring significant context often identify errors located in a completely different (and seemingly unassociated) location on the chip (e.g., a layout containing shorts or opens results in many errors that are not obviously associated to the location of a specific short or open). For this reason, in early design stages, it makes sense to ignore most connect rules. Similar large context rules include multi-patterning constraints, pitch checks derived from gridding rules, or pattern-based checks for patterns requiring a large area and/or lots of layers and geometries.

Rather than taking up an inordinate amount of engineer time in an effort to select the ‘right’ rules, the Calibre nmDRC Recon functionality automatically deselects checks that are known to require significant scope. However, to ensure flexibility and control of the process, engineers can specifically enable or disable any of these rules based on specified categories, individual check names or check group names, or even associated layers. This combination of default and local control means engineers can focus on finding the most obvious systemic design issues in very early iterations, while adding more rules as the design becomes cleaner.

In addition to reducing runtimes by minimizing the number of checks used, the Calibre nmDRC Recon functionality further shrinks runtime by reducing the total amount of the layout that is checked. A typical system-on-chip (SoC) design is built in parallel across multiple teams. Using the Calibre nmDRC Recon tool enables each team to focus on verifying only the elements that they have created before moving to a combined verification run. Also, when blocks in a chip-level design are not yet complete, checking these known ‘dirty’ blocks wastes time and generates millions of errors, obfuscating real issues at the top-level routing. Using gray-box techniques, the Calibre nmDRC Recon tool enables the run to ignore the contents of such blocks or cells, while still retaining specific pin layers and shapes at the cell periphery, as well as routes traversing across the cells from the top-level. This approach allows early identification of block placement problems or pin connection issues.

Of course, ignoring geometries when checking a layout can also introduce new errors. While many of these errors will be excluded through the Calibre nmDRC Recon rule de-selection process, a significant number of the remaining errors others can be automatically eliminated using advanced post-processing techniques during the debugging process.

Post-processing

Debugging issues are not limited to early design verification flows. In fact, debugging is a significant component of the overall time of a verification flow. Strategies and techniques that help design teams debug errors more quickly and efficiently can make the difference between hitting or missing tapeout schedules.

The Calibre Auto-Waivers tool lets engineers waive errors the foundry has deemed can be manufactured without yield impact. These can be known ‘false’ errors, results the design team does not want to see because they may resolve themselves in later stages, or ones that are likely to be fixed by someone else working on the larger design. Errors can be removed from results for a variety of reasons. Errors that have been seen and waived in smaller components, such as cells or blocks, can be automatically removed in subsequent runs where that component has been placed in a larger context, without worrying about hierarchical impacts. Errors can also be removed based on cell names or user-specified areas, which can be particularly useful in early verification flows on dirty or incomplete designs.

With enhanced post-processing, engineers may opt to remove results only if they are within a specified range with respect to the original rule constraints or based on associated result property attributes. Known false errors, such as those associated with fitting a skew or curved edge to a gridded database, can be automatically removed. There are even special approaches for unique rules, such as waiving specific density window locations. In all cases, of course, engineers can always review which errors were waived and why.

However, while automatically removing waived error results from the debugging process provides significant value, the debugging flow continues to challenge tapeout schedules. Exponential growth in design complexity, internal and external pressures on design cycle time, process advancements, and increases in both verification requirements and complexity are constantly driving the need for faster and more efficient physical verification tools. To take full advantage of new verification options and strategies introduced in recent years, designers must be able to quickly and easily analyze and understand all the extensive information they provide, so they can find and fix the root cause of errors in an efficient and accurate process.

The Calibre Auto-Waivers tool has been enhanced to not only help engineers identify and focus on specific errors of interest, but also to provide additional information to enable design teams to determine the best fix solutions. Enhanced post-verification processing of DRC results inserts additional properties to facilitate debugging flows. Hint information is automatically generated in dimensional check results to specify exactly how much to separate offending polygons or edges. Colormaps quickly identify regions of the layout with a significant number of results. Engineers can also specify window size and scope specific checks of interest.

In particular, understanding and debugging antennas errors is often a huge timesink for design teams. Foundry antenna decks often include checks in which there are multiple conditional constructs that define which equations should be used for calculating the antenna constraint. Failure depends on presence or absence of diodes, and the specific types of transistors and voltages associated. The Calibre Auto-Waivers infrastructure was enhanced to add debugging properties on failing nets and geometry, using clear and meaningful property names in the antenna output files. Nets are identified by their global net names, and the conditions for each violation are clearly detailed. The amount of damage inflicted and the corresponding diode area required to fix the violations are provided.

These types of post-processing capabilities enable design teams to optimize and minimize their debugging flows during both early design verification and later iterations.

Conclusion

Adding new and enhanced EDA functionality can help design teams eliminate or minimize unproductive and time-consuming stages in the design and verification flow. Narrowing the focus of error detection and debug in early design stages enables design teams to find and fix only those errors applicable to specific areas of the layout. Expanding the information provided during debugging activities facilitates faster debug and more accurate and optimized fixes. When compared to the traditional design flow where all data is combined and full sign-off DRC is run across the entire layout at each iteration, the combination of automated pre- and post-processing capabilities not only reduces DRC runtimes but also reduces debug time per iteration, and often the total number of iterations required, ultimately reducing total time to market while improving productivity.

Further reading

To learn more about the techniques and features described in this article, read these white papers:

Construct by correction with selective verification enhances productivity

Automated post-processing of DRC errors improves debugging productivity

About the author

John Ferguson is the product management director for Calibre DRC applications at Siemens Digital Industries Software. John has extensive experience in the area of physical design verification. He holds a B.Sc. degree in Physics from McGill University, an M.Sc. in Applied Physics from the University of Massachusetts, and a Ph.D. in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.