Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
Insights from research into reliability at Imec led to self-learning chips, security technologies, and finFET biosensors.
Shrinking process nodes, rising power efficiency goals and burgeoning device functionality are stretching existing DFR techniques to their limits. This scalable methodology looks to address the shortfall.
The time-dependent dielectric breakdown (TDDB) of inter-metal dielectrics on large-scale chips is becoming an increasingly important reliability issue across several semiconductor markets. This mechanism can cause early failures in use and is difficult to detect by traditional test, and hard to control by traditional reliability techniques.
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