serdes


May 11, 2018

Mixed-signal circuits push scaled CMOS at VLSI

The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , ,
February 13, 2018

HyperLynx update automates SerDes validation

Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.
Article  |  Topics: Blog Topics, Blog - PCB, - Product  |  Tags: , , , , , ,   |  Organizations:
February 14, 2017

Microsemi takes flash FPGAs to 28nm

Microsemi has launched a family of non-volatile FPGAs that use a 28nm process to increase density over the previous SmartFusion devices.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , ,   |  Organizations:
April 4, 2016

HyperLynx made broader and easier to use

HyperLynx from Mentor Graphics has moved into a new generation with more integrated features beyond PI and SI, and an easier to use GUI.
January 14, 2016

DesignCon 2016 preview: Mentor Graphics

HyperLynx leads the way for vendor at DesignCon with booth demos and a day-long modeling and analysis seminar.
June 10, 2013

Altera outlines process roadmap for ‘Gen 10’ FPGAs

Altera has disclosed a number of the features that will make it into the top end of its upcoming 'Generation 10' family of FPGAs.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations: , ,

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