IP reuse


June 27, 2017

Cliosoft aims to bring cooperation to design management

Cliosoft sees a merging of social features and design-data repositories as driving more efficient reuse in chipmakers, bringing them together in its recently launched DesignHub product line.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: ,
May 29, 2014
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IP takes center stage in push towards systems engineering

At DAC 2014, some 30 per cent of exhibitors are IP suppliers, offering design services or both, demonstrating how system-level design is about building on what has gone before.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: , , , , , ,
December 16, 2013

Synopsys puts physical IP prototypes into developers’ hands

Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations:
May 29, 2012

DAC 2012: OCP-IP moves to further ease reuse

The partnership's 3.1 specification is open for review, with performance enhancements and alignment to Accellera's IP-XACT for metadata
Article  |  Topics: Blog Topics, Blog - EDA, - ESL/SystemC, Standards  |  Tags: , , , ,   |  Organizations:
April 24, 2012

Xilinx revamps design software for new processes

Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , , , , ,   |  Organizations:

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