The Open Core Protocol International Partnership (OCP-IP) has become a key enabler for IP reuse and has just released its 3.1 specification to member review, alongside a related compliance document.
Some of the new features include:
- Flexible memory barriers
- Transaction counting parameters
- Transitions from OCP RTL.Conf files to the IP-XACT standard
- Cache coherence extensions for the new features.
Memory barriers will allow interfaces to use such techniques as write posting while using barrier commands “to enforce system ordering so that other cores will see the effects of critical memory updates in the expected order”.
Transaction counting enables buffer sizing, protocol checking and the formal verification of interfaces based on the maximum transaction count for each tag.
The alignment to IP-XACT takes over from OCP’s proprietary metadata format, making the integration of cores that use the standard easier across a far greater number of design environments.
OCP-IP has also just added 17 new traffic models to its transaction-level SystemC simulator, the Transaction Generator, for network-on-chip benchmarking. Eight of these are from Hong Kong University’s MCSL Benchmark Suite aimed at large systems in fields such as video processing, with 16, 32 and 64 defaults for the processing elements. The remaining nine have specialist use in multimedia, telecommunications and DRAM modeling.