Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.
Xilinx says it has made the first public release of its Vivado Design Suite – the reworked design environment for its sub-40mn programmable-logic devices that is based more heavily on concepts from the custom-IC world than its existing ISE toolset.
This newsletter highlights recently-added content on the site that addresses the connected areas of verification, prototyping and emulation. We’ve also added more overview EDA Guides on major design flow challenges.
At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, with updates to tools for physical design and verification.
Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.
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