This newsletter highlights recently-added content on the site that addresses the connected areas of verification, prototyping and emulation. We’ve also added more overview EDA Guides on major design flow challenges.
- Assertion-based verification: ABV claims ever greater adoption but is it being thoroughly implemented? These foundations will help you build an effective methodology.
- Verification IP: Proliferating I/O, memory standards and more are making VIP one of 2012’s liveliest markets, particularly as competition between Synopsys and Cadence intensifies.
- Using assertions in ‘elemental analysis’ for airborne hardware development – Part Two: The concluding installment describes the use of assertion-based verification to meet ‘elemental analysis’ and robustness testing for major aviation projects. Newcomers will find Part One here.
- Emulation delivers energy efficiencies and economies of scale: The technique’s benefits include more than just speed and visibility. It even has its ‘green’ side.
- Mentor boosts Veloce emulator: A new chip doubles the emulator’s capacity while a software update addresses historical limitations.
- No more spaghetti: Guest columnist Richard Pugh on how virtual lab environments can help you to leverage traditional emulation tasks more efficiently.
- FPGA prototyping: A hot topic because of the needs to cut time-to-market, manage the complexity of final silicon, and foster hardware/software co-design. But how do you chart the best course?
- What can FPGA-based prototyping do for you? A sample chapter from the Synopsys/Xilinx-authored FPGA-based Prototyping Methodology Manual goes deeper into the different strategies available, with valuable reference to real-world case studies.
- Xilinx revamps tool suite: The new Vivado software is architected for designs at 30nm and below.
- Synopsys updates Synplify: New release of the popular FPGA synthesis suite boosts efficiency and eases prototyping.
- Blue Pearl tightens integration to Synplify: Timing analysis constraints smooth the synthesis task.
- Guide: FinFETs
- Newsletters: Issue #3: Highlights from DATE 2012 and more