Blog Topics

The International Symposium on Quality Electronic Design (ISQED) enters its 13th edition later this month, running March 19-21 at Techmart in Santa Clara. Although ISQED traditionally concentrated on tools and IP blocks, its agenda has broadened as the industry has migrated to SoCs and full electronic systems where process and manufacturing interactions have come to […]

Our first email newsletter previews next month's Common Platform Technology Forum 2012 and features exclusive interviews with senior staff at Samsung, ARM and Cadence Design Systems.

Belgian research institute IMEC has stepped up its plans for 450mm development and now aims to have an operational full-flow pilot line by the end of 2015, according to president Luc Van den hove speaking at ISS Europe this week.

In the world of power semiconductors, not many companies try to go fabless. The tradeoffs between design and process offer many more options for system-level design, argued Infineon's Reinhard Ploss at the ISS Europe conference.

Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.

The International Solid-State Circuits Conference (ISSCC) this year provided an opportunity to see how the team that was first to put a finFET or trigate-based process into action on a multi-million transistor design did it.

The CDN Live series of Cadence Design Systems user conferences begins with its Silicon Valley edition at San Jose's Doubletree Hotel on March 12-13.

The high peak to average power ratios of LTE signals pose a power challenge to handset designers. Envelope tracking may help ease the problem.

Unmanned aerial vehicles have received a boost from a Senate vote, opening up opportunities for electronics designers.

A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy.