Blog Topics

Collaboration is becoming increasingly important to foundry companies as the development of advanced process nodes becomes more complex

Can pattern recognition improve deign rule checking at advanced nodes?

ARM has found that in its work on processor design looking at the system-design and process issues as well as the way software interacts with the machine can yield surprising results.

In this issue Chris Edwards introduces our interviews with key speakers at next week’s Common Platform Technology Forum, and highlights our presence at Cadence’s CDN Live and Europe’s DATE conferences. Dr Mukesh Khare of IBM Research discusses the ‘Innovation Pipeline’ beyond 14nm. Kelvin Low of GlobalFoundries describes how fabless companies can exploit 28nm processes. Michael […]

The International Symposium on Quality Electronic Design (ISQED) enters its 13th edition later this month, running March 19-21 at Techmart in Santa Clara. Although ISQED traditionally concentrated on tools and IP blocks, its agenda has broadened as the industry has migrated to SoCs and full electronic systems where process and manufacturing interactions have come to […]

Our first email newsletter previews next month's Common Platform Technology Forum 2012 and features exclusive interviews with senior staff at Samsung, ARM and Cadence Design Systems.

Belgian research institute IMEC has stepped up its plans for 450mm development and now aims to have an operational full-flow pilot line by the end of 2015, according to president Luc Van den hove speaking at ISS Europe this week.

In the world of power semiconductors, not many companies try to go fabless. The tradeoffs between design and process offer many more options for system-level design, argued Infineon's Reinhard Ploss at the ISS Europe conference.

Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.

The International Solid-State Circuits Conference (ISSCC) this year provided an opportunity to see how the team that was first to put a finFET or trigate-based process into action on a multi-million transistor design did it.