Intel takes considered route to FinFET
The International Solid-State Circuits Conference (ISSCC) this year provided an opportunity to see how the Intel team that was first to put a finFET or trigate-based process into action on a multi-million transistor design did it. And the organizers made sure it was among one of the first design papers on the schedule.
One thing that is clear from the work is that Intel did not try to make too many changes at once and create whole new custom circuits based on finFETs. Instead, the design team seems to have placed most of its faith in a lot of upfront analysis of transistor behaviour and circuit migration tools. Presenter Scott Siers referred to it as a “holistic design migration methodology”.
Migration was performed for register file and other custom circuits using either schematics or actual transistor layouts from the previous project. Despite the large change in transistor structure, Intel claims the use of migration saved about 15 per cent in project time. “Further, in order to ensure adequate timing margin for high-speed/high-voltage operation, an additional 7% was removed from the timing targets,” the Intel team noted in its paper.
One of the reasons for moving to finFETs was to provide designers with the option to trade speed against power and this was exploited in the 22nm Ivy Bridge processor through the use of three speed variants: “fast, nominal leakage devices; medium-speed, ‘quarter-leakage’ devices; and slower, ‘tenth-leakage’ devices”.
According to Intel: “High-frequency areas of the processor use ~30 per cent nominal and ~70 per cent quarter-leakage devices, while low speed areas use ~25 per cent quarter-leakage and ~75 per cent tenth-leakage devices.”
However, one problem with the finFET is its quantized drive strength: you cannot set W to an arbitrary amount, it has to be defined in terms of the number of fins. And the quantisation effect is worse for smaller transistors when the next step up from the minimum-size device is one that is twice as wide.
The Intel designers worked by playing safe and oversizing small transistors – any portion of a fin that might be considered optimum in terms of drive strength was scaled up to a full fin – rather than inserting transistors with less than optimal drive strength and risking the circuit not meeting timing.
“This yields much better timing with little power impact,” wrote Siers and colleages .”When possible during design closure, tools exchange excessive timing margin for the lower power options of either downsizing the device or converting it to a lower leakage variant.”
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