IP

SureCore is introducing an IP customization service intended to deliver SRAM cores tuned to specific power and performance requirements for wearable, wireless, augmented reality, and IoT devices.

Two keynote speakers have been announced for DVCon Europe 2018, which takes place next month.

Cadence has launched an AI processor using an designed to take advantage of the sparse structure of typical deep neural networks.

GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.

Research institute Leti and low-volume wafer service CMP are cooperating on a project to let fabless chipmakers explore the use of non-volatile resistive RAMs in their designs.

Faster PHYs needed to shift vast amounts of data around giant data centres.

The rapid growth of interest in machine learning and artificial intelligence has prompted Synopsys to bring all its AI IP together in a microsite and brochure.

In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.

The embedded FPGA is beginning to find a market, with communications leading the way but machine learning likely to drive further adoption.

FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.