IP

GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.

Research institute Leti and low-volume wafer service CMP are cooperating on a project to let fabless chipmakers explore the use of non-volatile resistive RAMs in their designs.

Faster PHYs needed to shift vast amounts of data around giant data centres.

The rapid growth of interest in machine learning and artificial intelligence has prompted Synopsys to bring all its AI IP together in a microsite and brochure.

In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.

The embedded FPGA is beginning to find a market, with communications leading the way but machine learning likely to drive further adoption.

FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.

After the moves by Cadence and Mentor, emulation in the cloud may only be the start of providing verification acceleration as a service.

Accellera has published the first release of the Portable Test and Stimulus Standard (PSS), with tools suppliers following up with software support.

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.