September 5, 2019
DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.
September 4, 2019
The IEDM has chosen a theme based around technologies for connected devices for its upcoming conference in December.
September 3, 2019
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
August 23, 2019
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
August 15, 2019
A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
July 31, 2019
Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
July 27, 2019
Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.
July 11, 2019
Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
July 8, 2019
Coventor has updated its SEMulator virtual-fab tool and added the ability to tune process windows based on simulation results.
July 4, 2019
The Bangalore conference has issued a last-minute call for panel proposals as technical paper submissions for the US edition get set to open next week.