Assessing the true cost of node transitions
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
EDA Topics
Using sequential equivalence to verify clock-gating strategies
Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
Doc Formal: The crisis of confidence facing verification
Why is verification still such a challenge in spite of all the technologies and techniques being brought to bear
Case study: Verifying and optimizing software for power on SoCs
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
Catch multi-patterning errors clearly at advanced nodes
How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Making security a profit center for silicon
The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.
Yield is money – and other truths of diagnosis-driven yield analysis
Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
Silicon photonics moves out of the shadows
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
How HLS is giving shape to glasses-free 3DTV
High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
Doc Formal: The evolution of formal verification – Part Two
Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.