Take advantage of the automated refactoring of design and verification code
Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.
EDA Topics
Achieving more efficient hierarchical DFT for Arm subsystems
Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Spreading the word on formal in Bangalore
Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
Optimize your database with duplicate data deletion
Whether you use OASIS or GDSII, unwanted duplicate cells can make their way into the final SoC database. Learn how to remove them.
Correct design and verification coding errors as you type
An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.
A new formal proof kit for RISC-V processors
Doc Formal describes a strategy developed by his company Axiomise to apply formal verification proofs to open-source processor for safety, security and reliability.
Speed up design and verification with a smaller layout
How to remove or extract portions of a layout for easier, more focused and faster project delivery.
Preparing for success at the next node with Calibre
How Mentor develops and works with partners to prepare each version of its Calibre DFM platform to be ready for the introduction of each new process node.
Why hyperlinks are essential for HDL debugging
Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.
How emulation’s virtual mode boosts productivity: Part Two
Part two of this feature describes three use-cases that exploit the VirtuaLAB technology in HDMI, PCIe and Ethernet designs.
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