Power intent files have increased efficiency and the use of an IDE can prevent them becoming outdated as a design evolves.
Autonomous vehicle functional verification needs to prove the predictable behavior, safety and security of complex SoCs and their associated software, sensors and actuators, demanding greater use of hardware emulation.
Parasitic extraction has to take more account of inductive effects as operating frequencies rise and feature sizes shrink in complex SoCs.
SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
Accellera's Portable Test and Stimulus standard provides powerful features for verification that is not meant to replace UVM but augment existing verification flows. Here is how portable stimulus and UVM interact.
The Portable Stimulus Standard helps overcome many of the verification challenges inherent in the strict requirements of ISO 26262.
Complex SoCs need systemic optimisation to achieve best time to results, enabled by the use of a unified RTL-to-GDSII flow underpinned by a unified data model.
Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.
Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
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