EDA Topics

September 3, 2021
Silicon Photonics - Verification - featim - sep21

Silicon photonics verification: Progress through adaptation

SiP promises advances in transmission speeds, bandwidth, accuracy and low power but verification requires careful evolution of existing tools.
July 20, 2021
Credit: laborotorio linux

Making sense of cloud EDA

How to carry out a sensible analysis of cloud EDA's potential, so you get the right tools and computational resources to deliver increasingly complex designs.
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June 25, 2021
Tina Durgia is a Product Manager for AMS verification at Siemens EDA and is responsible for the Solido Characterization Suite. Tina holds a Master’s degree in Electrical Engineering from Santa Clara University and has more than 13 years of experience in EDA across various digital design products including static timing analysis, place and route, logic synthesis and power analysis.

Use machine learning and visualization to accelerate Liberty file verification

Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
June 21, 2021
LEF abstract vs GDS

Out-of-sync data issues in parallel design flows need automated design integrity checks

Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
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May 31, 2021
Srinivas Velivala is a principal product manager with Calibre Design Solutions in Siemens EDA, a part of Siemens Digital Industries Software. His primary focus is the development of Calibre integration and interface tools and technologies. Before joining Siemens EDA, he designed high-density SRAM compilers. In addition to more than 12 years of design and product management experience, Srinivas holds a B.S. and M.S. in Electrical and Computer Engineering.

How you can decide what level of DRC you need when you need it

Using on-demand rule checks during place-and-route boosts efficiency and design quality.
May 3, 2021
Static checks May 2021

How automated static checks help verify complex circuits for better performance and reliability

Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
April 29, 2021

DVCon Europe best paper assesses clock design

The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
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April 9, 2021
FeatIm-spiral-methodology-bug-hunt

Spiral in on silicon bugs in six formal steps

The best paper winner at DVCon 2021 details a comprehensive methodology for making the best use of formal verification for bug hunting
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April 6, 2021

The path to full functional monitoring

Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
March 22, 2021

Silicon lifecycle solutions help you listen to your chip

SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.

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