Master parasitic extraction for leading-edge designs
A comprehensive guide to parasitics, how to perform parasitic extraction and the latest technologies available for this critical task.
EDA Topics
Debugging complex RISC-V processors
RISC-V adoption is growing fast as is the ecosystem around the open-source core. Hardware and software are now vital for appropriate debug.
TCP-Net and TCP-Net++ – a revolution in regression testing
TCP-Net is Test Case Prioritization using End-to-End Deep Neural Networks and addresses the challenges of today's software-rich projects.
The keys to ensuring IC quality
How the latest DFT techniques pave the way for quality and success for today's advanced designs.
How AI improves DFT, test and yield
Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.
Want to improve your user experience? Adopt a UX maturity model
A deep dive into the adoption, selection and implementation of models that boost productivity and customer loyalty.
BCI-ROM: a game-changer for electro-thermal design
The Boundary Condition Independent Reduced Order Model (BCI-ROM) provides vital help in addressing growing electro-thermal challenges in SPICE simulation.
Simplify and accelerate PV debug using default results data views
Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.
Improved power management and faster time to market?
We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
Refreshing the IEEE 1687 IJTAG family for today’s designs
Learn more about how the IJTAG family and associated standards are being enhanced for current challenges.