EDA Topics

April 3, 2024
Parasitic Extraction

Master parasitic extraction for leading-edge designs

A comprehensive guide to parasitics, how to perform parasitic extraction and the latest technologies available for this critical task.
March 29, 2024
RISC-V logo

Debugging complex RISC-V processors

RISC-V adoption is growing fast as is the ecosystem around the open-source core. Hardware and software are now vital for appropriate debug.
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February 29, 2024
TCP-Net Featim

TCP-Net and TCP-Net++ – a revolution in regression testing

TCP-Net is Test Case Prioritization using End-to-End Deep Neural Networks and addresses the challenges of today's software-rich projects.
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February 29, 2024

The keys to ensuring IC quality

How the latest DFT techniques pave the way for quality and success for today's advanced designs.
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February 8, 2024
Ron Press is Sr. Director of Technology Enablement for Tessent at Siemens EDA. As a 30-year veteran of the test and DFT industry, Ron has presented seminars on DFT and test throughout the world. He is a member of the International Test Conference (ITC) Steering Committee. a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing, glitch-free clock switching and on 3D DFT.

How AI improves DFT, test and yield

Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.
December 4, 2023
US featim

Want to improve your user experience? Adopt a UX maturity model

A deep dive into the adoption, selection and implementation of models that boost productivity and customer loyalty.
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November 30, 2023
BCI-ROM feature

BCI-ROM: a game-changer for electro-thermal design

The Boundary Condition Independent Reduced Order Model (BCI-ROM) provides vital help in addressing growing electro-thermal challenges in SPICE simulation.
October 19, 2023
Neel Natekar is a senior product engineer in the Design to Silicon division of Siemens Digital Industries Software. Prior to joining Siemens, Neel worked as a design engineer focusing on power delivery solutions for custom CPUs. He received a B.Eng. in Electronics and Telecommunications from the University of Mumbai, and an M.S. in Electrical Engineering, Circuits and Microsystems from the University of Michigan.

Simplify and accelerate PV debug using default results data views

Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.
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August 8, 2023
Jeff Wilson is a Product Management Director for DFM applications in the Calibre Design solutions organization at Siemens Digital Industries Software. Before joining Siemens, Jeff worked at Motorola and SCS. He holds a B.Sc. in design engineering from Brigham Young University and an MBA from the University of Oregon.

Improved power management and faster time to market?

We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
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May 30, 2023
IJTAG standards progress - featured image

Refreshing the IEEE 1687 IJTAG family for today’s designs

Learn more about how the IJTAG family and associated standards are being enhanced for current challenges.
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