EDA Topics

How virtual hardware can speed up many aspects of automotive system development, including architectural analysis, software development and verification

Hierarchical DFT is vital for large, complex designs. Users still to transition to the technique can nevertheless exploit its pattern reuse strategies as they move toward adoption.

Using formal core coverage to understand the effectiveness of formal coverage verification strategies in SoC design.

The equipment giant's Computational Process Control strategy takes a pragmatic approach to Industry 4.0 and is likely to influence EDA tools for incoming nodes.

DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).

DVCon中国大会主席刘红亮讨论了Accellera新增的DVCon中国ASIC设计和验证会议的看点。

Successful FPV of large designs requires that parts of the design are abstracted. Learning how and where to apply abstractions will result in more proven properties and more bugs found.

Addressing the challenge of achieving ASIL D certification of the functional safety of an SoC for use in the safety-critical path of an automotive system.

Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.

SSD controllers are becoming increasingly complex and as a result emulation is now the first choice for SSD verification. But your strategy must still meet five key criteria.