EDA Topics

January 27, 2017
Richard Pugh featured image SSD expert insight

The SSD memory revolution

Richard Pugh looks at how innovations highlighted during the recent International Memory Workshop are driving the solid state drive (SSD) market.
January 19, 2017
USB Type-C VIP featured image

USB Type-C: Verification challenges and solutions

The USB Type-C connector is versatile and already gaining traction in laptops, tablets and desktops. Here's how verification IP plays an important role in achieving the best implementation.
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January 18, 2017
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Are you formally connected?

To check the connectivity of an SoC, first you have to define what a connection is...
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January 16, 2017

An ISO 26262 approach to meeting the cost, quality, reliability, and integration needs of automotive ICs

Meeting ISO 26262 standards for automotive safety means applying a consistent approach throughout the design process. Here's how to start.
January 11, 2017
Derek Bouius

Three steps to implementing robust encryption

A look at the steps necessary to validate implementations of the cryptographic algorithms that are used to protect today’s devices and communications infrastructure.
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January 10, 2017
Silicon bring-up Tessent

Accelerate silicon bring-up in a bench-top environment

How a new software-led flow speeds silicon bring-up within the Tessent environment, including a Cypress Semiconductor case study.
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December 20, 2016
NVMe VIP featured image

Nine effective features of NVMe VIP for SSD storage

The open NVMe standard is helping non-volatile memory storage reach its true potential with increasingly rich verification support
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December 16, 2016
Robert Vamosi, CISSP and security strategist at Synopsys

Software validation strategies for connected cars

Software validation strategies will become increasingly important as cars become more complex, connected and autonomous.
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December 9, 2016
Featured image - analog design constraints

A new path for analog design constraints verification

Traditional techniques are being challenged by shortening design cycles and the effects of later process nodes.
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December 2, 2016

Hierarchical signoff of SoC designs at advanced process nodes

Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.