Verification specialist's DVCon activities are headlined by a panel on emulation and static verification.
Real Intent has lined up a mixture of technology and speed tests for its presence on Booth #1422 at the Design Automation Conference this year.
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
More than 20 new features and improvements are added to the static functional tool.
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
More lint rules, better SystemVerilog support, links to MATLAB and Simulink
Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.
Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
View All Sponsors