February 26, 2014
Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
October 30, 2013
Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
October 17, 2013
Formal techniques now underpin static verification approaches to checking clock domain crossings, constraints, reset and initialization states, and more
October 11, 2013
The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
September 19, 2013
Updated tool checks for correct design initialization, as well as managing X optimism and X pessimism at RTL or netlist level.
September 5, 2013
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
September 5, 2013
Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
July 8, 2013
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
June 18, 2013
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
May 14, 2013
Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.