October 30, 2013

The prospects for GALS: Real Intent’s view

Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
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October 17, 2013

Uptake of formal techniques in verification to be outlined in keynote

Formal techniques now underpin static verification approaches to checking clock domain crossings, constraints, reset and initialization states, and more
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October 11, 2013

Verification Futures rolls out in Europe next month

The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
September 19, 2013

Real Intent updates X verification tool

Updated tool checks for correct design initialization, as well as managing X optimism and X pessimism at RTL or netlist level.
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September 5, 2013

Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off

Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
September 5, 2013

SNUG Boston focuses on challenges of gigascale IC design

Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
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July 8, 2013

Real Intent links tools to Synopsys flows through in-Sync program

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
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June 18, 2013

Real Intent highlights hierarchical clock domain crossing with Meridian 5.0

SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Article  |  Topics: Blog - EDA, - RTL, Verification  |  Tags: , ,   |  Organizations: ,
May 14, 2013

Real Intent-DeFacTo sign-off flow for RTL combines CDC and DFT

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
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