Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
Formal techniques now underpin static verification approaches to checking clock domain crossings, constraints, reset and initialization states, and more
The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
Updated tool checks for correct design initialization, as well as managing X optimism and X pessimism at RTL or netlist level.
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
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