DAC2015: Real Intent at the Design Automation Conference
Real Intent has lined up a mixture of technology and speed tests for its presence on Booth #1422 at the Design Automation Conference (DAC) in San Francisco June 8-10, 2015.
Naturally, the company is keen to talk about the latest updates to both its Ascent tools for pre-synthesis, static RTL verification prior to synthesis and simulation as well as the Meridian lineup, which includes the recently launched Meridian Physical CDC. The new CDC tool is designed to stop metastability issues from creeping through to tapeout once all the post-synthesis logic changes have gone in, such as test insertion. If you can’t make it to DAC or want to see why that’s important, we have an article on the issues.
There will be technical presentations at the booth and you can set up appointments to meet with the specialists here. While you are there you can omplete a quick verification survey to be entered into drawings for a cool Roku 3 and a Kindle PaperWhite e-reader or take part in one of the company’s speed-test competitions.
Need for speed
You can take the wheel of a favorite high-performance race car to celebrate faster verification and design, in one of two GRID Arcade Racing Simulators, and get a License to Speed. And if you visit both Real Intent and OpenText (Booth #1414), Real Intent’s “License-to-Speed” partner at DAC, you can get a ticket stamped by both companies to enter drawings for $100 Amazon Gift Cards, a GoPro camera, a Bose wireless sound system, and Beats Studio wireless headphones.
As well as on-booth activity, Real Intent also invites attendees to Room #304 to the pavilion panel “View Scalable Verification: Evolution or Revolution?” on Wednesday, June 10 from 4:30-6pm Co-organized by Real Intent, this panel is moderated by Brian Bailey, technology and EDA editor of Semiconductor Engineering. Experts from Freescale Semiconductor, NVIDIA, Qualcomm, Hewlett-Packard and ARM will discuss whether existing industry verification standards and methodologies for verifying IP blocks and subsystems can be extended to address SoC integration and system-level functionality of embedded systems, or if new approaches are needed.
