Chipmaker

October 4, 2012

IEF: Open source hardware to muscle into data centers

Open-source hardware is going to change the way people buy computing capacity for data centers, says LSI's Rob Ober
October 4, 2012

IEF: Achronix plans embedded FPGA push

Achronix plans to use the FPGA fabric that it has developed for standalone products to be fabbed through Intel as the springboard for an embedded-FPGA offering.
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA, - General  |  Tags: , , , ,   |  Organizations: , ,
October 4, 2012

IEF: Samsung wants a skunk-works

Samsung Electronics is setting up a center in Silicon Valley to try to develop technologies that the company hopes will ultimately drive volume for its chipmaking operation.
August 6, 2012

TSMC joins Intel as ASML investor to accelerate availability of EUV, 450mm lithography

TSMC follows Intel in taking a stake in ASML to accelerate development of EUV and 450mm lithography equipment.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , ,   |  Organizations: , ,
August 6, 2012

Aart de Geus on the changing face of EDA

The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.
Article  |  Topics: Commentary, Design to Silicon, Blog - EDA, Embedded, - General, Verification  |  Tags: , , ,   |  Organizations: , ,
July 26, 2012

Xilinx extends Vivado availability

Xilinx says it has made the first public release of its Vivado Design Suite – the reworked design environment for its sub-40mn programmable-logic devices that is based more heavily on concepts from the custom-IC world than its existing ISE toolset.
Article  |  Topics: Blog - EDA, - Product  |  Tags:   |  Organizations:
June 14, 2012

Strained silicon beats TSV stress in 3DICs

Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.
June 12, 2012

Doping gives finFETs threshold control

You want finFETs with different threshold voltages on the same SoC? Forget what the FD-SOI guys tell you: it's possible. At least with a certain amount of performance loss, say IBM and GlobalFoundries.
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June 11, 2012

FD-SOI to get foundry push in ST deal

A deal between GlobalFoundries and STMicroelectronics has answered the question as to where ICs based on an FD-SOI process can be made, and not just for ST.
Article  |  Topics: Blog Topics, Design to Silicon, Digital/analog implementation  |  Tags:   |  Organizations: ,
June 6, 2012

DAC 2012: Intel’s Ivy Bridge chip chop shop

Intel's Ivy Bridge series of processors were designed from the outset to be split apart and recombined to create variants of the base platform, Intel architecture project manager Brad Heaney explained during the Wednesday keynote session at DAC 2012.
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