Chipmaker

TSMC follows Intel in taking a stake in ASML to accelerate development of EUV and 450mm lithography equipment.

The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.

Xilinx says it has made the first public release of its Vivado Design Suite – the reworked design environment for its sub-40mn programmable-logic devices that is based more heavily on concepts from the custom-IC world than its existing ISE toolset.

Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.

You want finFETs with different threshold voltages on the same SoC? Forget what the FD-SOI guys tell you: it's possible. At least with a certain amount of performance loss, say IBM and GlobalFoundries.

A deal between GlobalFoundries and STMicroelectronics has answered the question as to where ICs based on an FD-SOI process can be made, and not just for ST.

Intel's Ivy Bridge series of processors were designed from the outset to be split apart and recombined to create variants of the base platform, Intel architecture project manager Brad Heaney explained during the Wednesday keynote session at DAC 2012.

Could subthreshold circuitry help extend the reach of power gating? Mike Muller said during his DAC keynote that the technique looks viable.

Could more flexible licensing strategies for cloud-based EDA enable more efficient simulation and a new wave of business models?

Blue Pearl is building alliances to bring its timing analysis tools to more users.