Chipmaker

Design security is a major target for Microsemi’s update to its Igloo series of flash memory-based FPGAs, which add an ARM-oriented memory subsystem.

Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.

Atmel has launched its first family of microcontrollers based on ARM's Cortex M0+ with features to ease PCB design and provide programmable serial ports.

Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.

Altera has disclosed a number of the features that will make it into the top end of its upcoming 'Generation 10' family of FPGAs.

The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.

The effort needed in timing signoff could lead to a shift in design towards asynchronous techniques unless advanced OCV technologies improve.

The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.

Xilinx and TSMC are forming a single engineering team to accelerate development of a family of finFET-based field programmable gate arrays (FPGAs).

A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference