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EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.

Plunify will demonstrate its new Kabuto tool that recommends RTL fixes for FPGA designs at the Design Automation Conference.

Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.

Local EDA vendor Austemper will be demonstrating a comprehensive functional safety design tool suite in Austin next week.

Accellera has released an Early Adopter version of the upcoming Portable Stimulus Specification.

Semiconductor supplier Microsemi has used the Eclipse open-source IDE platform to develop a Windows-based toolchain for CPUs that supports the RISC-V instruction set.

Oski Technology will offer a range of daily presentations at its DAC 2017 and useful technical advice in the main conference program.

EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.

Verific has acquired the Invio custom-tool development environment developed by Invionics Software.

Parser specialist will highlight work with a low power startup and new features for platforms supporting UPF.