DAC 2017 preview: Austemper Design

By TDF Staff |  No Comments  |  Posted: June 16, 2017
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Austin’s own Austemper Design will be serving up ‘Texas-sized’ demos on its booth (#1420) as the Design Automation Conference (DAC 2017) returns to its home town next week (June 18-22).

During the DAC 2017 exhibition days (June 19-21), Austemper’s focus will be on an end-to-end Functional Safety Tool Suite for SoC, ASIC and IP designs. It is particularly targeted at applications in the¬†automotive, industrial, medical and enterprise markets.

The tool suite covers a spectrum of functional safety engineering requirements, including safety analysis, safety synthesis to augment design structures, and safety verification. It has four components, all of which will be available for review.

  • SafetyScope implements functional safety estimates based on a mission profile and set of diagnostic coverage mechanisms.
  • Annealer automates a hitherto manual and error-prone approach to handle memories, register files, FIFOs or entire processing units.
  • RadioScope provides fine-grained safety synthesis capabilities.
  • KaleidoScope delivers a parallel fault simulator with hybrid simulation capabilities.

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