VHDL

July 22, 2014

Real Intent puts the accent on debug with new Ascent IIV release

More than 20 new features and improvements are added to the static functional tool.

Article | Topics: Product, RTL, Verification | Tags: functional verification, static verification, SystemVerilog, Verilog, VHDL, x propagation | Organizations: RealIntent

March 16, 2012

DATE notebook: Aldec builds in more support for VHDL methodology

Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL

Article | Topics: Conferences, Design to Silicon, Blog - EDA | Tags: DATE 2012, OS-VVM, SystemVerilog, UVM, verification, VHDL

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