Directed self assembly may offer similar benefits to EUV, process modeling study says
Directed self assembly techniques may offer similar benefits to EUV lithography, especially for DRAM makers, says SPIE conference paper
Directed self assembly techniques may offer similar benefits to EUV lithography, especially for DRAM makers, says SPIE conference paper
ARM has gone back to the 32bit realm for its latest Cortex-A processor core, aiming the device at a new generation of low-cost platforms inspired by the success of the Raspberry Pi as well as wearables.
Verification specialist’s DVCon activities are headlined by a panel on emulation and static verification.
Mentor Graphics chairman and CEO Wally Rhines will deliver the DVCon keynote as the vendor sets a deep agenda for the conference.
ARM and Ceva have both aimed at the need for to juggle control code and DSP in the upcoming LTE-Advanced and 5G with their latest processor core architectures.
The Calibre vendor will have a strong technical presence at the leading lithography conference taking place in late February in San Jose.
Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.
The Multicore Association has started work on standardizing a set of APIs that aim to simplify communications between processors in heterogeneous multicore SoCs
A look at techniques to trap complex errors caused by signals crossing clock, reset and power domains is the focus of this upcoming webinar
HyperLynx leads the way for vendor at DesignCon with booth demos and a day-long modeling and analysis seminar.