Hybrid chip links ARM core with C-programmable deterministic peripherals

By Luke Collins |  No Comments  |  Posted: October 24, 2013
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XMOS has integrated its xCORE configurable, deterministic multicore microcontroller technology with an ultra-low-power ARM Cortex-M3 processor to create a low-power ‘programmable system on chip’ that draws on the ARM code base.

The xCORE-XA (for eXtended Architecture) is targeted at applications which fall in the power/performance gap between top-end microcontrollers and low-end FPGAs.

Nigel Toon, XMOS CEO, said: “There’s a lot of stuff in the middle that overlaps with our capability.”

Discussing the reasons for integrating an ARM core alongside XMOS’ own microcontroller architecture, Toon added: “ARM is the gorilla in this market these days – obviously a very nice gorilla – and there’s a big library of code for their devices. We thought ‘Are we really going to go out and say XCORE replaces ARM?’ It struck us that the right thing to do was to embrace ARM.”

To do so, XMOS has struck a deal to use the low-power Cortex-M3 based Gecko core technology developed by Energy Micro, recently acquired by Silicon Labs. 

Geir Forre, vice president and general manager of Silicon Labs’ microcontroller products, said: “The result of this partnership is a completely new type of programmable system on chip product that combines our industry-leading energy-friendly technology with a unique level of system configuration and performance.”

Deterministic peripherals

The xCORE architecture includes multiple logical processor cores, a set of I/O resources that can be programmed to support a variety of protocols, a deterministic scheduler, an interconnect fabric, and working memory. What the company calls xSOFT ip can be used to program the onchip resources to work as anything from a 64bit DSP to an EtherCAT interface. Integrating this with the Energy Micro core (initially using multiple die in one package) to create the xCORE-XA chips adds the ARM support and flash memory.

the xCORE-XA architecture (Source: XMOS)

Figure 1 the xCORE-XA architecture (Source: XMOS)

XMOS says that the new architecture will enable embedded system designers to use high-level software to configure a device with the interfaces and peripherals needed for their design, as well as to re-use existing ARM binary code and take advantage of ultra-low energy peripherals. Designers can add real-time data-plane plus control processing and DSP blocks, using multiple xCORE processor cores, and then use the ARM available to run larger control-plane processing software such as communication protocol stacks, standard graphics libraries, or complex monitoring systems.

Energy management

The new chips also apply the energy-management modes developed by Energy Micro.

“This is where a partnership with Energy Micro made senses because they have already developed some of these states,” said Toon.

  • In the lowest energy shut-down state the chip draws 100nA at 3.3V, and can be woken by a GPIO signal or reset in 160μs.
  • A deep sleep mode draws a typical 1μA and can be woken by a real-time clock or low-power 32kHz peripherals in 2μs.
  • A processor-sleep mode allows the peripherals to run autonomously and draws a typical 50μA.
  • A low-power mode delivers 50MIPS of processor performance for a typical 10mA.
  • The performance mode offers 500MIPS for a typical 50mA.

The first XA device, the XA-U8-1024, has eight 32bit processors (seven xCORE logical cores plus an ARM Cortex-M3 processor), 192Kbyte of SRAM, and 1024Kbyte of Flash. It includes a low-energy USB interface, ultra low-energy peripherals and analogue functions including ADC, DAC, op-amps and capacitive sensing comparators. Future variants, offered without the low-energy USB 2.0 interface, will have six or eight cores with Flash sizes ranging from 512Kbyte to 1024Kbyte.


XMOS will roll support for the ARM code development process into its xTIMEcomposer Suite of development tools, including offering a GCC compiler for the ARM code.

Co-development of code for the ARM core and xCORE (Source: XMOS)

Figure 2 Co-development of code for the ARM core and xCORE (Source: XMOS)

This will enable developers to program the ARM core in one window while configuring the xCORE peripheral interfaces and functions in the other, both using high level languages such as C or C++.  Designers will also be able to use existing Silicon Labs software tools to access code libraries and documentation for the ARM® Cortex™ M3 processor core.

The debug instrumentation currently available for xCORE designs will be extended to cover the ARM side of the design.

Co-debug of the ARM and xCORE code (Source: XMOS)

Figure 3 Co-debug of the ARM and xCORE code (Source: XMOS)

XMOS says the applications for the xCORE-XA include in the nascent ‘Internet of Things’ market; for advanced peripherals such as things that connect to tablets or PCs; in real-time networking; and  in smarter control systems, for example for multi-axis robotics.


Toon said that ideal applications would draw on the chip’s combination of low power, high available performance and determinism In the audio market, for example, a simple MP3 playback device might underutilize the chip whereas multichannel, high-quality audio mixing would be a better fit. In robotic vision systems, he argued, a microcontroller might be able to handle basic edge detection but more sophisticated algorithms would need more computing power: “We can deliver the compute at a power consumption level which is very compelling.”

Over the longer term, Toon plans to develop more powerful variants of the architecture as the market demands, as well as moving  its digital and mixed-signal portions on to newer processes: he points that because the performance of the xCORE architecture is deterministic it should be possible to decide on the application performance that you need and then reduce the supply voltage to achieve just that.

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