UPF group moves to consider system-power issues
The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
Author Archives: Chris Edwards
Embedded world ‘needs EDA’s models’
The EDA industry has a way to capture the embedded software market, analyst Gary Smith said ahead of DAC. But it’s not through tools – it’s through models.
Latest version of IEEE 1801/UPF available for free
The latest revision of the IEEE 1801 Unified Power Format standard for verifying low-power designs has been made available through the IEEE Get Program.
TSMC and Xilinx forge tighter bonds to speed up finFET port
Xilinx and TSMC are forming a single engineering team to accelerate development of a family of finFET-based field programmable gate arrays (FPGAs).
DAC 2013 Preview VIII: Low-power design
Sessions at the DAC 2013 conference in Austin, Texas focus on low-power design and engineering low-energy systems from the system level down to physical.
Automotive benchmark puts focus on power consumption
Vehicle-maker Volkswagen is putting its weight behind a set of microcontroller benchmarks that focus on energy consumption rather than performance.
Cadence tackles timing signoff with Tempus
Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.
TVS expands VIP library
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
SureCore picks up grant for low-power, nanometer SRAM IP
Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.
Altera buys into power management with Enpirion
Altera has bought fabless power-management specialist Enpirion in an expansion intended to support its core business of FPGAs.