Altera buys into power management with Enpirion
Altera has bought fabless power-management specialist Enpirion in an expansion intended to support its core business of FPGAs.
Author Archives: Chris Edwards
CDNLive EMEA: Embedded processors could surge past mobile at ARM in a few years
ARM could see shipments of embedded processors based on its architecture begin to outpace its rump market in mobile within four years if growth continues at current levels.
CDNLive EMEA: Cadence brings IEEE 1801 into simulation update
Cadence Design Systems has decided to embrace IEEE 1801, derived from the Unified Power Format (UPF), providing support alongside the Common Power Format (CPF).
CDNLive EMEA: Cadence to buy Evatronix
Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.
NXP captures tools for ARM micros with Code Red buy
NXP Semiconductors has decided to buy tools supplier Code Red Technologies to help build up software support for its ARM-based microcontrollers.
GlobalFoundries to take Infineon flash to 40nm for MCUs
Globalfoundries will port Infineon Technologies’ flash technology to 40nm to support the manufacture of automotive and security microcontrollers (MCUs).
CDNLive EMEA looms
CDNLive EMEA opens 6 May, providing delegates with an opportunity to find out what their peers are doing with Cadence Design Systems’ tools in real projects.
AMD targets software scalability with embedded x86
AMD has stepped back into the market for embedded processors with a quad core design derived from its desktop APUs, which combine a general-purpose x86 subsystem with a GPU.
Accellera publishes tag standard for soft IP
Accellera Systems Initiative has published version of 1.0 of its Soft IP Tagging standard for adding licensing information to RTL and other design files.
ARM intros single-use licence for Big-Little
ARM has decided to put together a package deal for some of the components that will let prospective customers implement a multiprocessor subsystem in a single SoC design