ARM buys securable display controller
ARM has agreed to buy from Cadence Design Systems the display controller IP cores developed by recent acquisition Evatronix.
Author Archives: Chris Edwards
IP providers make plans for the internet of things
ARM and Synopsys both plan to make inroads to the internet of things with their IP strategies.
CDNLive Boston to tackle mixed-signal design, host exhibit
Taking place in Chelmsford, MA on 27 August, the conference will feature user-authored papers, tutorials, a designer expo and keynotes from Cadence and IBM.
Group plans better tools for multicore
A Japanese government-funded project has become the basis of a standard proposed by the Multicore Association that may provide a better way of supporting development for multicore systems.
Three Accellera proposals aim for better TLM
Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.
Electrically aware Virtuoso aims to head off physical issues
Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.
Xilinx tapes out for first of 20nm-generation FPGAs
Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.
nVidia to license GPU technology as IP cores
Graphics chipmaker nVidia has said it plans to license as IP cores some of its technology in the hope of building up a customer base among other chipmakers and systems houses developing their own SoCs.
Microsemi focuses on security with Igloo2 FPGAs
Design security is a major target for Microsemi’s update to its Igloo series of flash memory-based FPGAs, which add an ARM-oriented memory subsystem.
Atmel bridges 8 and 32bit gap with ARM M0+ family
Atmel has launched its first family of microcontrollers based on ARM's Cortex M0+ with features to ease PCB design and provide programmable serial ports.