Mentor now scales Xpedition’s multi-board PCB capabilities
The latest update to Mentor's market-leading PCB design suite aims to unify system definitions across multiple tools to reduce errors.
Yearly Archives: 2014
10Gbit/s USB 3.1 IP and verification support on the way
USB 3.1 IP, verification IP, virtual development kit build on Synopsys' USB 3.0 DesignWare and supporting ecosystem
imec and Coventor partner for 7nm process development
Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab
Cadence tool automates library creation of analog macros
Cadence Design Systems has launched an analog simulation tool designed to speed up the characterization of mixed-signal macros that can then be used to create the Liberty representations needed for full-chip signoff.
Synopsys combines cell-aware, slack-based test to find transient defects, adds eFlash support
Two approaches to greater reliability revealed in Synopsys ATPG and DesignWare updates
Cadence targets ISO 26262 with verification support
Cadence Design Systems has built a verification environment around its vManager software for ICs and systems that need to conform to the ISO 26262 safety standard.
IBM pays GlobalFoundries to take on chipmaking operation
GlobalFoundries is to acquire IBM's fabs in a deal that sees the server maker pay the foundry $1.5bn over five years and agree to exclusivity to 10nm.
ARC core focuses on embedded Linux applications
Synopsys updates ARC core to improve support for embedded Linux and other advanced operating systems such as Android
Still time to get to European design and verification conference
DVCon Europe brings design and verification insights to Munich next week.
Minimal 32bit IP cores tackle connected devices market
Minimal IP cores are meant to serve broader market than IoT, using revised instruction set to increase code density, save on chip memory and enable security
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