Cadence Design Systems has launched an analog simulation tool designed to speed up the characterization of mixed-signal macros that can then be used to create the Liberty representations needed for full-chip signoff.
Virtuoso Liberate AMS is intended to characterize commonly used mixed-signal blocks such as phase-locked loops (PLLs), data converters, high-speed transceivers and I/Os. The tool takes post-layout netlists of the mixed-signal macros and uses their associated parasitic elements, which may number in the millions in today’s processes. Cadence claims the tool produces results 20 times faster than traditional “divide and conquer” FastSPICE simulation methods but can support SPICE-level accuracy.
The Liberate tool uses what Cadence calls a hybrid partitioning approach to identify required arcs and dynamically exercise them to characterize large mixed-signal blocks. This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterizes using SPICE-level accuracy to create the library models.
“Prior to using Virtuoso Liberate AMS, the characterization process for mixed-signal blocks was an error-prone manual process,” said Darren Engelkemier, vice president of digital IC engineering at Aquantia, a user of pre-release versions of the tool. “With Virtuoso Liberate AMS, our design teams were able to automate this task by eliminating netlist processing and getting more accurate and reliable data especially for our custom cells with non-standard structures at circuit-level.”