A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
'Design for yield' is a familiar term, but the challenges in today's increasingly large projects make a refresher on what it offers particularly timely.
By taking the circuit supply voltage close to that of the threshold voltage or even below, it is possible to optimize low-power VLSI design. But there are pitfalls.
Design for security is an emerging topic in hardware engineering demanding a more holistic approach that traditional cryptographic implementation.
IC designers are becoming increasingly worried about the possibility of third parties inserting malicious 'trojan' circuitry into their ICs.
The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
The 10nm generation is the follow-on process to the 14nm/16nm node and will provide a choice of either finFET or planar FD-SOI architectures. But the likely absence of EUV will increase costs.
The 14nm and 16nm processes cover a range of technologies and are designed to succeed the 20nm generation. They bring with them a number of design challenges.
The encryption chain for today's highly collaborative designs needs to be managed with care.
Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
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