The first DVCon China will take place on April 19th at the Zhang Jiang Parkyard Hotel in Shanghai. The event joins Accellera’s existing editions of its series of design and verification conferences in the US, Europe and India.
China has a large number of design engineers, and that number is growing fast. There are many major local and global companies with Chinese design centers. There is also rapid growth in the number of start-up ASIC design companies. All of these can benefit from DVCon’s mixture of technical sessions, tutorials, an exhibition and two keynotes based around standards developed by Accellera and industry best practices
Andy Liu, based at AMD’s Shanghai design office, is DVCon China’s first general chair. We spoke to him about the reasons for launching the conference and what attendees can expect to learn at it.
First, we looked at why now is a good time to launch a China edition of DVCon.
“Accellera is a leader in the field of creating standards for ASIC functional design and verification,” he said. “There are, for example, System Verilog, SystemC and now UVM. These standards are popular among semiconductor companies worldwide, including Chinese companies of course.
“Meanwhile, DVCon is the primary conference series for ASIC functional design and verification conference. Accellera is creating a global environment for professional development by creating a worldwide network of conferences, now including DVCon China.
“And it is also important that, unlike most other conferences for the semiconductor industry, DVCon focuses on the actual practice of design and verification. That is a blue-ocean aspect for China.”
The initial DVCon China is a single-day event, but the organizes have packed a lot into the program. There are two keynotes speakers, six tutorials, 22 posters, an exhibition, and six technical sessions. The keynote speakers are Wally Rhines, chairman and CEO of Mentor Graphics, and Yong Fu, group director of the Verification Group at Synopsys.
“Almost all the hot topics in ASIC design and verification are covered in the program. We have low power, UVM, GPU modeling, IP reuse, formal verification, mixed-signal, fault simulation, system design and debug strategies,” said Liu.
“The most attractive items will set out the latest progress in Accellera standards development, best practices developed at well-known ASIC design companies and EDA companies, perspectives from Industry leaders, and front-end research shared by famous universities such as Fudan, Tsinghua.
“And I would particularly highlight the content on UVM because that has now been adopted by the IEEE as a standard, after its development by Accellera.”
DVCon China – building for the future
Ultimately Liu would like to see DVCon China establish a platform for greater cooperation across China’s corporate, academic and internal standards-setting communities. The first edition has drawn on expertise and knowledge from its sister conferences. But is still a locally-led event. Most of the 35 Technical Committee members are from China. Their job has been to make sure that the conference has specific relevance to the local audience.
Nevertheless, Liu sees DVCon China as an opportunity for his country to now both learn from but also give something back to the global semiconductor design community.
As a result, he hopes that DVCon’s arrival in China will encourage greater local involvement in international standards development.
“I believe more and more Accellera standards will become IEEE standards, like UVM,” said Liu. “In general, I would say that engaging with the Accellera process will allow China to sync up with global standard development closely, and make its voice heard while making its contribution to that development. The importance of that is self-evident,” Liu said.
Program details and registration are available at the official DVCon website.