Still using Moore’s Law to beat up on the automotive industry?
These days, when it comes to innovation: The car's the star - not the stooge.
IC Implementation
How to maximize productivity with faster, high-capacity RTL synthesis
New RTL synthesis tools such as Oasys-RTL have greater capacities and shorter runtimes as well as allowing more attention to be spent on achieving QoR
Floorplanning complex SoCs with multiple levels of physical hierarchy
How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
How new RTL floorplanning techniques speed physical design
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
FPGA design for functional safety
Using triple modular redundancy, error detection and correction, and 'safe' FSMs to ensure greater functional safety in FPGA-based designs
2016 – A continuation of change
Dr Walden Rhines, Mentor Graphics chairman and CEO, looks forward to the trends that will shape 2016 in the semiconductor industry.
Timing analysis shifts to statistical
The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
Mixed-signal designs prepare for coloring at 10nm
The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.
Cadence’s path to digital implementation on 10nm
The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.
FPGA-based prototyping 3: Which board do I need?
Part three of our series looks at the choices you face as you decide whether to build or buy a board.
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