The authors descirbe a new signature-based approach to resolving the content of layouts in GDSII, OASIS and other formats.
Artificial intelligence and machine learning require the performance and flexibility offered by embedded FPGA (eFPGA) technology.
A new version of the automotive safety standard arrives later this year. Review the main updates and see how it will combine with the incoming SOTIF autonomous driving standard.
In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
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