A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
ESD has always been a major issue but with increasing densities and growing die sizes it is becoming a higher order concern. Automation and vizualization can help manage the task.
The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
How Siemens PAVE 360 platform leverages emulation to deliver the exhaustive test required for the incoming generation of autonomous vehicles.
Power intent files have increased efficiency and the use of an IDE can prevent them becoming outdated as a design evolves.
Parasitic extraction has to take more account of inductive effects as operating frequencies rise and feature sizes shrink in complex SoCs.
SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
The Portable Stimulus Standard helps overcome many of the verification challenges inherent in the strict requirements of ISO 26262.
Complex SoCs need systemic optimisation to achieve best time to results, enabled by the use of a unified RTL-to-GDSII flow underpinned by a unified data model.
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